In order to assure their proper functioning, electrical circuits need to be supplied with power supply levels. Various circuits may require several power supply voltages and a ground reference of OV. The voltage levels utilized by the circuits need to be constant and free of noise in order for the circuits to function properly.
Power distribution systems utilized within a chip may be constructed from a solid plane, mesh plane or a plurality of wires. An ideal plane will embody zero resistance in addition to supplying clean constant voltage levels to electrical circuits. Electrical circuits draw large currents in order to perform electrical operations. These currents are supplied by a system power supply via a power distribution system. When the power distribution system is not ideal, it cannot instantaneously supply the needed current. This is caused by a time constant or delay needed to charge the power distribution impedance Z, where the supplied voltage V is V=ZI, and I is the current drawn by the circuits. The actual geometrical limitation in electrical circuit structures generates a non-ideal power distribution impedance, Zeff. The charging of this Zeff will result in a power level “droop” or “delta-I noise” or “simultaneously-switching-noise.”
A typical analysis of a power distributor analyzes the entire power distribution as one entire distributed circuit. Such models may be extremely large when millions of circuits exist on a conventional integrated circuit chip or in the instance when many chips are packaged together to form an electronic system. Due to the shear volume of circuitry to analyze, models such as these require long and large numerical computations. For this reason, computations can only replace the actual electrical sources with ideal linear current sources that draw current from the non-ideal power distribution. Therefore, only linear circuit solvers that analyze the noise waveforms can be employed for reasonable computation times.
The implementation of a simplified analysis can only give approximate noise estimations due to the fact that the interaction with other noise sources in actual electrical circuits cannot be accurately captured. Moreover, the effect of noise on the timing of electrical signal propagation can only be approximated.
As the clock frequencies of present electrical circuits is being raised toward 10 GHz and the number of transistor circuits is going from 400 million in the year 2003 to a foreseeable 2200 million in the year 2010, the expected delta-I noise is expected to rise to excessive levels. In order to contain such noise and prevent logic circuit failures, accurate analysis is needed of the power distribution effective impedance Zeff, with the use of actual non-linear circuits. This analysis needs to be performed with a fast turnaround time in order to allow for many iterations in a design cycle. Further, new techniques need to be developed that can be implemented in CAD tools that accurately verify or predict the delta-I noise in short time.
As system complexity and speed increase, both accuracy and run times are required to improve in order to have multiple iterations in the design cycle of multi-GHz operation electronic systems. The high level of integration afforded in high-performance systems places large processor units and memory either on the same chip or on the same chip carrier. Communication between processor units and memory involves hundreds of electrical circuits switching simultaneously and sending information. These hundreds of circuits require large current sources that are supplied with very fast transition rates, or             ⅆ      I              ⅆ      t        .
On chip carriers, the power distribution supplying the power supply levels or rails is in the form of solid conductor planes or mesh planes. These planes have low resistance. A connection to these planes is established through coarse interconnecting conductors called vias. Due to this connection, the effective impedance of the power distribution is mostly inductive, and thus the delta-I noise generated is V=ZeffI=j2πLeffI or V=NLeff      V    =                  NL        eff            ⁢                        ⅆ          I                          ⅆ          t                      ,wherein N is the number of driver circuits and f is the frequency of operation. The effective inductance Leff is calculated by modeling the entire chip carrier power planes and vias. A large circuit analysis of this type is very time consuming. On chip power supply levels are fed into the chip from the supporting chip carrier on coarse solder balls or wire bonds. The electric circuits are a few microns in size, while the solder balls are on 200–400 μm pitch.
Power distribution on chip is made out of a plurality of conducting wires that are placed on many thin layers, being interconnected by small vertical conductors also called vias. The spatial distance between the solder balls and the actual circuit contacts will generate an effective Zeff for the power distribution that has both high resistance (R) and inductance (L). Moreover, resistance and inductance are frequency-dependent in this case. Present analysis systems of on-chip power distributions analyze the entire group of power wires and vias for chips that are 20×20 mm in size. Such on-chip power distribution analyses are not frequency-dependent because of the size of the problem. The resistance and inductance at one frequency point are used, thus introducing inaccuracy in the noise prediction.
Current on-chip analyses require many days of modeling time for one configuration of power distribution. Modeling sensitivity analysis or design change benefits cannot be evaluated because of long computation times.
Such analysis can only use approximate linear current sources to represent the actually electrical circuits. The resultant noise is added linearly with other noise sources like crosstalk and reflections that occur on the wires connecting the circuits. Such linear addition is not accurate, therefore, usually the wires are analyzed separately from the power distribution.
The effect of delta-I noise on signal propagation timing is calculated with simplified formulas, for example Vnoise/(dI/dt). This is very approximate and ignores the non-linear behavior of actual electrical circuits with noisy power rails. Such analyses can do limited assessment of the impact of the chip carrier power distribution on the on-chip power distribution because both models are extremely large.
For the above stated reasons modeling accurate, frequency-dependent, and non-linear simulations are not implemented in CAD tools due to size and time limitations. Many chips are designed without accurate analysis and noise-caused failures prevent product release to customers.